In a typical conventional 4T+2R SRAM process, the two resistors in each SRAM cell are implemented using polysilicon resistors. Because the resistors are used as the load devices for the SRAM cell, the polysilicon resistors are implemented to have a high resistance value, thereby decreasing power dissipation. In a typical process to form the SRAM cell load resistors (commonly referred to as the poly-load process), polysilicon is deposited on both sides of the wafer.
In these conventional SRAM fabrication processes, the polysilicon on the backside of the wafer is susceptible to peeling during subsequent processing of the wafer (i.e., backside polysilicon peeling). Of course, the backside polysilicon peeling is undesirable because the peeled polysilicon is a source of particle contamination in the wafers, cassette and equipment. As is well known, particle contamination generally decreases yields, thereby increasing production costs.
FIG. 1 is a flow chart illustrating a typical SRAM process that is susceptible to backside polysilicon peeling. In a step 10, a poly-load film is formed on a substrate using a standard process. For example, the poly-load film may be formed by using a standard furnace process, which results in the poly-load film being formed on both sides of the wafer.
Then, an interlayer dielectric (ILD) layer is formed on the poly-load film as indicated by the block 12. Generally, the ILD layer is formed by depositing a BPTTEOS layer on the frontside of the wafer using a standard CVD process. However, in practice, a thin native oxide layer is formed on the backside poly-load film as a result of a thermal treatment performed after depositing the poly-load film.
Then a step 14 is performed in which the ILD layer is patterned and etched to form contact holes through the ILD layer so that the load resistors may be electrically connected to the transistors of the SRAM cell. In a typical process, a metal layer is used to interconnect the load resistors. Thus, in a next step 16, a standard pre-metal dip process is performed to clean the contact holes formed in the step 14. Unfortunately, this pre-metal dip also attacks the native oxide layer which was formed on the backside polysilicon. Because this native oxide layer is very thin, portions of the backside polysilicon are exposed after the pre-metal dip.
In a next step 18, a metal layer (metall or M1 layer) is deposited on the ILD layer. The metall layer is then patterned and etched to form the interconnect in a step 20. After the metall layer is etched, the photoresist layer used to pattern the metall layer is stripped. In most standard stripping processes, the wafer is dipped in an acidic etching solution. This acidic solution will then also attack the unprotected poly-load layer on the backside of the wafer, resulting in the backside polysilicon peeling.